Transistor step-header



y 3, 1966 D. R. BRIGGS ETAL 3,249,683

TRANS IS TOR S PEP-HEADER Filed Dec. 19, 1963 e .wwm r T B R M em w V..0d DE nited rate 3,249,683 TRANSISTOR STEP-HEADER Doyce R. Briggs andEdward P.

assignors to Texas em, a corporation of Delaware Filed Dec. 19, 1963,Ser. No. 331,717

Claims. (Cl. 17450.56)

provide for this protection, the device itself is usually encapsulatedin an air-tight, hermetically sealed enclosure,

usually referred to as the header, and a cover The semiconducwithin theenclos- Containers of this type provide benefits of standardization; h wver, they also create some problems in the production of transistors.Welding or soldering the can to the header, for instance,

of avoiding the contamination is by coldwelding, a form of pressurebonding that seals the header and can without the aid of heat. The useof cold welding itself, on the other hand, presents various problems. inparticular, and th hermetically sealed enclosure.

Another object is to provide a pressure weldable enclosure.

l is a cross-sectional view of a header with a can in place beforewelding;

FIGURE 21: shows a portion of the flange area of the header and canbefore welding; FIGURE 2b shows the same portion as FIGURE 2a afterwelding;

FIGURE 3 shows a pictorial top view of the header. Referring now toFIGURE 1, th

3,249,683 Patented May 3, 1966 pass through openings in the header topsurface, but are held away therefrom in a fixed name, as Kovar.

pressure weldable other metals may be used for the outer layer 4, it ISdesirable to use a metal having good heat conductive properties whichwill semiconductor device.

Below the glass 6 is groove 7 which extends around the innercircumference of the URE 2a is a portion of the header-can assemblyshown in FIGURE 1. The relative position of theheader and the should benoted that the vertical wall of the header has an offset, or step,

The flange portions the step, ing-in of device enclosed therein.

FIGURE 3 shows a top view of the header showing the locations of theleads and the general header.

as defined in the appended claims.

What is claimed is: 1. A semiconductor encapsulating device comprising:

O terminating in a peripheral flange region shell; a body of insulatingmaterial encased tallic shell, and a plurality of leads passing throughsaid insulating body and said shell and electrically insulated from saidshell.

3. A stepped wall semiconductor header made of a plurality of metalliclayers clad together, said closing an insulating material passingtherethrough and electrically insulated from said header and said headerhaving groove extending around said stepped wall below said insulatingmaterial, said insulating material being completely contained above saidgroove.

4. A stepped wall semiconductor header made of a plurality of metalliclayers clad together, said header enclosing an insulating material witha plurality of leads passing therethrough and electrically insulatedfrom said header and said header having an interior groove extendingaround said stepped wall below said insulating material, said groovebeing effective in preventing glass from flowing below said step therebypreventing damage to said insulating material.

References Cited by the Examiner UNITED STATES PATENTS FOREIGN PATENTS2/1956 Australia.

OTHER REFERENCES IRE Transactions on Electron Devices," No. 3, July1959, p. 312 relied on.

vol. ED-6,

ROBERT K. SCHAEFER, Primary Examiner. JOHN F. BURNS, Examiner.

W. B. FREDRICKS, I. F. RUGGIERO,

Assistant Examiners.

1. A SEMICONDUCTOR ENCAPSULATING DEVICE COMPRISING: A METALLIC SHELLHAVING A PLURALITY OF LAYERS CLAD TOGETHER ENCASING A BODY OF INSULATINGMATERIAL; AND A PLURALITY OF LEADS PASSING THROUGH SAID BODY ANDELECTRICALLY ISOLATED FROM SAID SHELL, SAID METALLIC SHELL HAVING A TOPPORTION AND A VERTICAL WALL PORTION WITH A STEPPED REGION EXTENDINGCOMPLETELY AROUND SAID WALL AND TERMINATING IN A FLANGED PERIPHERALREGION.